U.S. patent application Ser. No. 12/403,195 (CNTR.2475), filed Mar. 12, 2009, which is hereby incorporated by reference in its entirety, discloses an adaptive power throttling feature that attempts to provide the user the most performance possible while still staying below a maximum power consumption (P) over a defined time interval (T). The P and T values are typically specified by the manufacturer of the system that incorporates the microprocessor that includes the adaptive power throttling feature. The microprocessor knows the frequency at which it can operate indefinitely without consuming more than P Watts and typically operates at this frequency (Xp). (In one embodiment, the frequency at the operating point Xp corresponds to the well-known P-state commonly referred to as P0.) However, at numerous sub-intervals of T (referred to as bins), the microprocessor calculates the average power consumed (A) over the most recent T time and compares A with P. If A is sufficiently less than P (i.e., the microprocessor has power “credits”), the microprocessor may decide to run itself at a frequency that is higher than Xp.
The introduction of dual cores on a single microprocessor package introduces complexity to the adaptive power throttling feature, or power credit feature. This is because the system manufacturer imposes the P and T requirement on a microprocessor package basis, not on a per-core basis. However, the independent cores will likely consume different power over a given T. First, the operating system changes the operating points (e.g., P-states and C-states) independently for each core such that the cores consume different power. Furthermore, the software workload will likely be different on the two cores. Additionally, the independent cores may reach their bin intervals at different points in real time. Nevertheless, the P and T requirements must be met for the microprocessor package as a whole.